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80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers product specification 1996 aug 16 integrated circuits ic20 data handbook
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 2 1996 aug 16 8530169 17187 description the philips 80c31/80c51/87c51 is a high-performance microcontroller fabricated with philips high-density cmos technology . the cmos 8xc51 is functionally compatible with the nmos 8031/8051 microcontrollers. the philips cmos technology combines the high speed and density characteristics of hmos with the low power attributes of cmos. philips epitaxial substrate minimizes latch-up sensitivity. the 8xc51 contains a 4k 8 rom (80c51) eprom (87c51), a 128 8 ram, 32 i/o lines, two 16-bit counter/timers, a five-source, two-priority level nested interrupt structure, a serial i/o port for either multi-processor communications, i/o expansion or full duplex uar t, and on-chip oscillator and clock circuits. in addition, the device has two software selectable modes of power reductioneidle mode and power-down mode. the idle mode freezes the cpu while allowing the ram, timers, serial port, and interrupt system to continue functioning. the power-down mode saves the ram contents but freezes the oscillator, causing all other chip functions to be inoperative. features ? 8031/8051 compatible 4k 8 rom (80c51) 4k 8 eprom (87c51) romless (80c31) 128 8 ram two 16-bit counter/timers full duplex serial channel boolean processor ? memory addressing capability 64k rom and 64k ram ? power control modes: idle mode power-down mode ? cmos and ttl compatible ? five speed ranges at v cc = 5v 12mhz 16mhz 24mhz 33mhz ? five package styles ? extended temperature ranges ? otp package available pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 rst rxd/p3.0 txd/p3.1 int0 /p3.2 int1 /p3.3 t0/p3.4 t1/p3.5 p1.7 wr /p3.6 rd /p3.7 xtal2 xtal1 v ss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p2.5/a13 p2.6/a14 p2.7/a15 psen ale/prog ea /v pp p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 v cc ceramic and plastic dual in-line package ceramic and plastic lead chip carrier 6 1 40 7 17 39 29 18 28 plastic quad flat pack 44 34 1 11 33 23 12 22 su00001 see page 3 for qfp and lcc pin functions.
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 3 ceramic and plastic leaded chip carrier pin functions lcc 6 1 40 7 17 39 29 18 28 pin function 1 nc* 2 p1.0 3 p1.1 4 p1.2 5 p1.3 6 p1.4 7 p1.5 8 p1.6 9 p1.7 10 rst 11 p3.0/rxd 12 nc* 13 p3.1/txd 14 p3.2/int0 15 p3.3/int1 pin function 16 p3.4/t0 17 p3.5/t1 18 p3.6/wr 19 p3.7/rd 20 xtal2 21 xtal1 22 v ss 23 nc* 24 p2.0/a8 25 p2.1/a9 26 p2.2/a10 27 p2.3/a11 28 p2.4/a12 29 p2.5/a13 30 p2.6/a14 pin function 31 p2.7/a15 32 psen 33 ale/prog 34 nc* 35 ea /v pp 36 p0.7/ad7 37 p0.6/ad6 38 p0.5/ad5 39 p0.4/ad4 40 p0.3/ad3 41 p0.2/ad2 42 p0.1/ad1 43 p0.0/ad0 44 v cc su00002 * do not connect plastic quad flat pack pin functions pin function 1 p1.5 2 p1.6 3 p1.7 4 rst 5 p3.0/rxd 6 nc* 7 p3.1/txd 8 p3.2/int0 9 p3.3/int1 10 p3.4/t0 11 p3.5/t1 12 p3.6/wr 13 p3.7/rd 14 xtal2 15 xtal1 pin function 16 v ss 17 nc* 18 p2.0/a8 19 p2.1/a9 20 p2.2/a10 21 p2.3/a11 22 p2.4/a12 23 p2.5/a13 24 p2.6/a14 25 p2.7/a15 26 psen 27 ale/prog 28 nc* 29 ea /v pp 30 p0.7/ad7 pin function 31 p0.6/ad6 32 p0.5/ad5 33 p0.4/ad4 34 p0.3/ad3 35 p0.2/ad2 36 p0.1/ad1 37 p0.0/ad0 38 v cc 39 nc* 40 p1.0 41 p1.1 42 p1.2 43 p.13 44 p1.4 pqfp 44 34 1 11 33 23 12 22 su00003 * do not connect logic symbol port 0 port 1 port 2 port 3 address and data bus address bus secondary functions rxd txd int0 int1 t0 t1 wr rd rst ea /v pp psen ale/prog v ss v cc xtal1 xtal2 su00004
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 4 ordering information philips north america eprom drawing number romless rom drawing number temperature range o c and package 1 freq mhz sc87c51ccf40 0590b 0 to +70, ceramic dual in-line package, uv 3.5 to 12 sc87c51cck44 1472a 0 to +70, ceramic leaded chip carrier , uv 3.5 to 12 sc87c51ccn40 sot129-1 sc80c31bccn40 sc80c51bccn40 sot129-1 0 to +70, plastic dual in-line package, otp 3.5 to 12 sc87c51cca44 sot187-2 sc80c31bcca44 sc80c51bcca44 sot187-2 0 to +70, plastic leaded chip carrier , otp 3.5 to 12 sc87c51ccb44 sot307-2 sc80c31bccb44 sc80c51bccb44 sot307-2 0 to +70, plastic quad flat pack, otp 3.5 to 12 sc87c51acf40 0590b 40 to +85, ceramic dual in-line package, uv 3.5 to 12 sc87c51acn40 sot129-1 sc80c31bacn40 sc80c51bacn40 sot129-1 40 to +85, plastic dual in-line package, otp 3.5 to 12 sc87c51aca44 sot187-2 sc80c31baca44 sc80c51baca44 sot187-2 40 to +85, plastic leaded chip carrier , otp 3.5 to 12 sc87c51acb44 sot307-2 sc80c31bacb44 sc80c51bacb44 sot307-2 40 to +85, plastic quad flat pack, otp 3.5 to 12 sc87c51cgf40 0590b 0 to +70, ceramic dual in-line package, uv 3.5 to 16 sc87c51cgk44 1472a 0 to +70, ceramic leaded chip carrier , uv 3.5 to 16 sc87c51cgn40 sot129-1 sc80c31bcgn40 sc80c51bcgn40 sot129-1 0 to +70, plastic dual in-line package, otp 3.5 to 16 sc87c51cga44 sot187-2 sc80c31bcga44 sc80c51bcga44 sot187-2 0 to +70, plastic leaded chip carrier , otp 3.5 to 16 sc87c51cgb44 sot307-2 sc80c31bcgb44 sc80c51bcgb44 sot307-2 0 to +70, plastic quad flat pack, otp 3.5 to 16 sc87c51agf40 0590b 40 to +85, ceramic dual in-line package, uv 3.5 to 16 sc87c51agn40 sot129-1 sc80c31bagn40 sc80c51bagn40 sot129-1 40 to +85, plastic dual in-line package, otp 3.5 to 16 sc87c51aga44 sot187-2 sc80c31baga44 sc80c51baga44 sot187-2 40 to +85, plastic leaded chip carrier , otp 3.5 to 16 sc87c51agb44 sot307-2 sc80c31bagb44 sc80c51bagb44 sot307-2 40 to +85, plastic quad flat pack, otp 3.5 to 16 sc87c51cpf40 0590b 0 to +70, ceramic dual in-line package, uv 3.5 to 24 sc87c51cpk44 1472a 0 to +70, ceramic leaded chip carrier , uv 3.5 to 24 sc87c51cpn40 sot129-1 sc80c31bcpn40 sc80c51bcpn40 sot129-1 0 to +70, plastic dual in-line package, otp 3.5 to 24 sc87c51cpa44 sot187-2 sc80c31bcpa44 sc80c51bcpa44 sot187-2 0 to +70, plastic leaded chip carrier , otp 3.5 to 24 sc87c51apf40 0590b 40 to +85, ceramic dual in-line package, uv sc87c51apn40 sot129-1 sc80c31bapn40 sc80c51bapn40 sot129-1 40 to +85, plastic dual in-line package, otp 3.5 to 24 sc87c51apa44 sot187-2 sc80c31bapa44 sc80c51bapa44 sot187-2 40 to +85, plastic leaded chip carrier , otp 3.5 to 24 sc87c51cyf40 0590b 0 to +70, ceramic dual in-line package, uv 3.5 to 33 sc87c51cyk44 1472a 0 to +70, ceramic leaded chip carrier , uv 3.5 to 33 sc87c51cyn40 sot129-1 sc80c31bcyn40 sc80c51bcyn40 sot129-1 0 to +70, plastic dual in-line package, otp 3.5 to 33 sc87c51cya44 sot187-2 sc80c31bcya44 sc80c51bcya44 sot187-2 0 to +70, plastic leaded chip carrier , otp 3.5 to 33 1. otp = one t ime programmable eprom. uv = uv erasable eprom 2. sot311 replaced by sot307-2.
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 5 ordering information (continued) philips romless (order number) romless (marking number) rom drawing number temperature range o c and package 1 freq mhz pcb80c31-2 n pcb80c31bh2-12p pcb80c51bh-2p sot129-1 0 to +70, plastic dual in-line package, otp 0.5 to 12 pcb80c31-2 a pcb80c31bh2-12 wp pcb80c51bh-2wp sot187-2 0 to +70, plastic leaded chip carrier , otp 0.5 to 12 pcb80c31bh2-12h pcb80c51bh-2h sot307-2 2 0 to +70, plastic quad flat pack, otp 0.5 to 12 pcb80c31-3 n pcb80c31bh3-16p pcb80c51bh-3p sot129-1 0 to +70, plastic dual in-line package, otp 1.2 to 16 pcb80c31-3 a pcb80c31bh3-16 wp pcb80c51bh-3wp sot187-2 0 to +70, plastic leaded chip carrier , otp 1.2 to 16 pcb80c31bh3-16h pcb80c51bh-3h sot307-2 2 0 to +70, plastic quad flat pack, otp 1.2 to 16 pcf80c31-3 n pcf80c31bh3-16p pcf80c51bh-3p sot129-1 40 to +85, plastic dual in-line package, otp 1.2 to 16 pcf80c31-3 a pcf80c31bh3-16 wp pcf80c51bh-3wp sot187-2 40 to +85, plastic leaded chip carrier , otp 1.2 to 16 pcf80c31bh3-16h pcf80c51bh-3h sot307-2 2 40 to +85, plastic quad flat pack, otp 1.2 to 16 PCA80C31BH3-16P pca80c51bh-3p sot129-1 40 to +125, plastic dual in-line package 1.2 to 16 pca80c31bh3-16 wp pca80c51bh-3wp sot187-2 40 to +125, plastic leaded chip carrier 1.2 to 16 pcb80c31-4 n pcb80c31bh4-24p pcb80c51bh-4p sot129-1 0 to +70, plastic dual in-line package, otp 1.2 to 24 pcb80c31-4 a pcb80c31bh4-24 wp pcb80c51bh-4wp sot187-2 0 to +70, plastic leaded chip carrier , otp 1.2 to 24 pcb80c31bh4-24h pcb80c51bh-4h sot307-2 2 0 to +70, plastic quad flat pack, otp 1.2 to 24 pcf80c31-4 n pcf80c31bh4-24p pcf80c51bh-4p sot129-1 40 to +85, plastic dual in-line package, otp 1.2 to 24 pcf80c31-4 a pcf80c31bh4-24 wp pcf80c51bh-4wp sot187-2 40 to +85, plastic leaded chip carrier , otp 1.2 to 24 pcf80c31bh4-24h pcf80c51bh-4h sot307-2 2 40 to +85, plastic leaded chip carrier , otp 1.2 to 24 pcb80c31-5 n pcb80c31bh5-30p pcb80c51bh-5p sot129-1 0 to +70, plastic dual in-line package 1.2 to 33 pcb80c31-5 a pcb80c31bh5-30 wp pcb80c51bh-5wp sot187-2 0 to +70, plastic leaded chip carrier 1.2 to 33 pcb80c31-5 b pcb80c31bh5-30h pcb80c51bh-5h sot307-2 2 0 to +70, plastic quad flat pack 1.2 to 33
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 6 block diagram psen ea /v pp ale/prog rst xtal1 xtal2 v cc v ss port 0 drivers port 2 drivers ram addr register ram port 0 latch port 2 latch rom/eprom register b acc stack pointer tmp2 tmp1 alu timing and control instruction register pd oscillator psw port 1 latch port 3 latch port 1 drivers port 3 drivers program address register buffer pc incre- menter program counter dptr pcon scon tmod tcon th0 tl0 th1 tl1 sbuf ie ip interrupt, serial port and timer blocks p1.0p1.7 p3.0p3.7 p0.0p0.7 p2.0p2.7 su00005
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 7 pin description pin no. mnemonic dip lcc qfp type name and function v ss 20 22 16 i ground: 0v reference. v cc 40 44 38 i power supply: this is the power supply voltage for normal, idle, and power-down operation. p0.00.7 3932 4336 3730 i/o port 0: port 0 is an open-drain, bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory . in this application, it uses strong internal pull-ups when emitting 1s. port 0 also outputs the code bytes during program verification in the 87c51. external pull-ups are required during program verification. p1.0p1.7 18 29 40-44, 13 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). port 1 also receives the low-order address byte during program memory verification. p2.0p2.7 2128 2431 1825 i/o port 2: port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application, it uses strong internal pull-ups when emitting 1s. during accesses to external data memory that use 8-bit addresses (mov @ri), port 2 emits the contents of the p2 special function register. p3.0p3.7 1017 11, 1319 5, 713 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (see dc electrical characteristics: i il ). port 3 also serves the special features of the 80c51 family, as listed below: 10 11 5 i rxd (p3.0): serial input port 11 13 7 o txd (p3.1): serial output port 12 14 8 i int0 (p3.2): external interrupt 13 15 9 i int1 (p3.3): external interrupt 14 16 10 i t0 (p3.4): timer 0 external input 15 17 11 i t1 (p3.5): timer 1 external input 16 18 12 o wr (p3.6): external data memory write strobe 17 19 13 o rd (p3.7): external data memory read strobe rst 9 10 4 i reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal diffused resistor to v ss permits a power-on reset using only an external capacitor to v cc . ale/prog 30 33 27 i/o address latch enable/program pulse: output pulse for latching the low byte of the address during an access to external memory . in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency , and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory . this pin is also the program pulse input (prog ) during eprom programming. psen 29 32 26 o program store enable: the read strobe to external program memory . when the device is executing code from the external program memory , psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory . ea /v pp 31 35 29 i external access enable/programming supply v oltage: ea must be externally held low to enable the device to fetch code from external program memory locations 0000h to 0fffh. if ea is held high, the device executes from internal program memory unless the program counter contains an address greater than 0fffh. this pin also receives the 12.75v programming supply voltage (v pp ) during eprom programming. xtal1 19 21 15 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 18 20 14 o crystal 2: output from the inverting oscillator amplifier .
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 8 table 1. 80c52/80c54/80c58 special function registers symbol description direct address bit address, symbol, or alternative port function msb lsb reset value acc* accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h auxr# auxiliary 8eh ao xxxxxxx0b auxr1# auxiliary 1 (note 2) a2h wupd 0 dps xxxx00x0b b* b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h dptr: data pointer (2 bytes) dph data pointer high 83h 00h dpl data pointer low 82h 00h af ae ad ac ab aa a9 a8 ie* interrupt enable a8h ea ec et2 es et1 ex1 et0 ex0 00h bf be bd bc bb ba b9 b8 ip* interrupt priority b8h pt2 ps pt1 px1 pt0 px0 x0000000b b7 b6 b5 b4 b3 b2 b1 b0 iph# interrupt priority high b7h pt2h psh pt1h px1h pt0h px0h x0000000b 87 86 85 84 83 82 81 80 p0* port 0 80h ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ffh 97 96 95 94 93 92 91 90 p1* port 1 90h t2ex t2 ffh a7 a6 a5 a4 a3 a2 a1 a0 p2* port 2 a0h ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ffh b7 b6 b5 b4 b3 b2 b1 b0 p3* port 3 b0h rd wr t1 t0 int1 int0 txd rxd ffh pcon# 1 power control 87h smod1 smod0 gf1 gf0 pd idl 00xx0000b d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov p 00h saddr# slave address a9h 00h saden# slave address mask b9h 00h sbuf serial data buffer 99h xxxxxxxxb 9f 9e 9d 9c 9b 9a 99 98 scon* serial control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00h sp stack pointer 81h 07h 8f 8e 8d 8c 8b 8a 89 88 tcon* timer control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h cf ce cd cc cb ca c9 c8 t2mod# timer 2 mode control c9h t2oe dcen xxxxxx00b th0 timer high 0 8ch 00h th1 timer high 1 8dh 00h tl0 timer low 0 8ah 00h tl1 timer low 1 8bh 00h tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00h * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs. reserved bits. 1. reset value depends on reset source. 2. available only on sc80c51.
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 9 oscillator characteristics xtal1 and xt al2 are the input and output, respectively , of an inverting amplifier . the pins can be configured for use as an on-chip oscillator, as shown in the logic symbol. t o drive the device from an external clock source, xt al1 should be driven while xt al2 is left unconnected. there are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. however , minimum and maximum high and low times specified in the data sheet must be observed. reset a reset is accomplished by holding the rst pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. t o insure a good power-up reset, the rst pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. idle mode in idle mode, the cpu puts itself to sleep while all of the on-chip peripherals stay active. the instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. the cpu contents, the on-chip ram, and all of the special function registers remain intact during this mode. the idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. power-down mode in the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. only the contents of the on-chip ram are preserved. a hardware reset is the only way to terminate the power-down mode. the control bits for the reduced power modes are in the special function register pcon. t able 2 shows the state of i/o ports during low current operating modes. table 2. external pin status during idle and power-down modes mode program memory ale psen port 0 port 1 port 2 port 3 idle internal 1 1 data data data data idle external 1 1 float data address data power-down internal 0 0 data data data data power-down external 0 0 float data data data rom code submission when submitting rom code for the 80c51, the following must be specified: 1. 4k byte user rom data 2. 64 byte rom encryption key (sc80c51 only) 3. rom security bits (sc80c51 only). address content bit(s) comment 0000h to 0fffh data 7:0 user rom data 1000h to 101fh key 7:0 rom encryption key 1020h sec 0 rom security bit 1 1020h sec 1 rom security bit 2 security bit 1: when programmed, this bit has two ef fects on masked rom parts: 1. external movc is disabled, and 2. ea# is latched on reset. security bit 2: when programmed, this bit inhibits v erify user rom.
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 10 electrical deviations from commercial specifications for extended t emperature range (87c51) dc and ac parameters not included here are the same as in the commercial temperature range table. dc electrical characteristics t amb = 40 c to +85 c, v cc = 5v 10%, v ss = 0v (philips north america sc87c51); for sc87c51 (33mhz only), t amb = 0 c to +70 c, v cc = 5v 5% t amb = 40 c to +85 c, v cc = 5v 10%, v ss = 0v (pcb80c31/51 and pcf80c31/51 philips parts only) test limits symbol parameter conditions min max unit v il input low voltage, except ea (philips north america) 0.5 0.2v cc 0.15 v v il input low voltage, except ea (philips) 0.5 0.2v cc 0.25 v v il1 input low voltage to ea 0.5 0.2v cc 0.45 v v ih input high voltage, except xtal1, rst 0.2v cc +1 v cc +0.5 v v ih1 input high voltage to xtal1, rst 0.7v cc +0.1 v cc +0.5 v i il logical 0 input current, ports 1, 2, 3 v in = 0.45v 75 m a i tl logical 1-to-0 transition current, ports 1, 2, 3 v in = 2.0v 750 m a i cc power supply current: v cc = 4.55.5v cc active mode 1 @ 16mhz (philips pcb80c31/51, pcf80c31/51) 25 ma active mode @ 12mhz (philips north america sc87c51) 20 ma idle mode 2 @ 16mhz (philips pcb80c31/51, pcf80c31/51) 6.5 ma idle mode @ 12mhz (philips north america sc87c51) 5 ma power-down mode 3 (philips pcb80c31/51, pcf80c31/51) 75 m a power-down mode (philips north america sc87c51) 50 m a notes: 1. the operating supply current is measured with all output pins disconnected; xt al1 driven with t r = t f = 10ns; v il = v ss + 0.5v; v ih = v cc 0.5v; xtal2 not connected; ea = rst = port 0 = v cc . 2. the idle mode supply current is measured with all output pins disconnected; xt al1 driven with t r = t f = 10ns; v il = v ss + 0.5v; v ih = v cc 0.5v; xtal2 not connected; ea = port 0 = v cc ; rst = v ss. 3. the power-down current is measured with all output pins disconnected, xt al2 not connected, ea = port 0 = v cc ; rst = v ss. absolute maximum ratings 1, 2, 3 parameter rating unit operating temperature under bias 0 to +70 or 40 to +85 c storage temperature range 65 to +150 c voltage on ea /v pp pin to v ss 0 to +13.0 v voltage on any other pin to v ss 0.5 to +6.5 v maximum i ol per i/o pin 15 ma power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 w notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the ac and dc electrical characteristics section of this specification is not implied. 2. this product includes circuitry specifically designed for the protection of its internal devices from the damaging ef fects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted.
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 11 dc electrical characteristics t amb = 0 c to +70 c or 40 c to +85 c, v cc = 5v 20%, v ss = 0v (pcb80c31/51 and pcf80c31/51) (12, 16, and 24mhz versions) t amb = 0 c to +70 c or 40 c to +85 c, v cc = 5v 10%, v ss = 0v (87c51 12, 16, and 24mhz versions) (pcb80c31/51 33mhz version); for sc87c51 (33mhz only) t amb = 0 c to +70 c, v cc = 5v 5% test limits symbol parameter conditions min typical 1 max unit v il input low voltage, except ea 7 0.5 0.2v cc 0.1 v v il1 input low voltage to ea 7 0 0.2v cc 0.3 v v ih input high voltage, except xtal1, rst 7 0.2v cc +0.9 v cc +0.5 v v ih1 input high voltage, xtal1, rst 7 0.7v cc v cc +0.5 v v ol output low voltage, ports 1, 2, 3 11 i ol = 1.6ma 2 0.45 v v ol1 output low voltage, port 0, ale, psen 11 i ol = 3.2ma 2 0.45 v v oh output high voltage, ports 1, 2, 3, ale, psen 3 i oh = 60 m a, i oh = 25 m a i oh = 10 m a 2.4 0.75v cc 0.9v cc v v v v oh1 output high voltage (port 0 in external bus mode) i oh = 800 m a, i oh = 300 m a i oh = 80 m a 2.4 0.75v cc 0.9v cc v v v i il logical 0 input current, ports 1, 2, 3 7 v in = 0.45v 50 m a i tl logical 1-to-0 transition current, ports 1, 2, 3 7 see note 4 650 m a i li input leakage current, port 0 v in = v il or v ih 10 m a i cc power supply current: 7 active mode @ 12mhz 8 (philips) active mode @ 12mhz 5 (philips north america) idle mode @ 12mhz 9 (philips) idle mode @ 12mhz (philips north america) power-down mode 10 (philips and philips north america) see note 6 11.5 1.3 3 18 19 4.4 4 50 ma ma ma ma m a r rst internal reset pull-down resistor (philips north america) 50 300 k w (philips) 50 150 k w c io pin capacitance 12 10 pf notes: 1. t ypical ratings are not guaranteed. the values listed are at room temperature, 5v . 2. capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. in the worst cases (capacitive loading > 100pf), the noise pulse on the ale pin may exceed 0.8v . in such cases, it may be desirable to qualify ale with a schmitt trigger , or use an address latch with a schmitt t rigger strobe input. i ol can exceed these conditions provided that no single output sinks more than 5ma and no more than two outputs exceed the test conditions. 3. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9v cc specification when the address bits are stabilizing. 4. pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in is approximately 2v. 5. i ccmax at other frequencies (for philips north america parts) is given by: active mode: i ccmax = 1.43 x freq + 1.90; idle mode: i ccmax = 0.14 x freq +2.31, where freq is the external oscillator frequency in mhz. i ccmax is given in ma. see figure 8. 6. see figures 9 through 12 for i cc test conditions. 7. for philips north america parts when t amb = 40 c to +85 c or philips parts when t amb = 40 c to +125 c, see dc electrical characteristics table on previous page. 8. the operating supply current is measured with all output pins disconnected; xt al1 driven with t r = t f = 10ns; v il = v ss + 0.5v; v ih = v cc 0.5v; xtal2 not connected; ea = rst = port 0 = v cc . 9. the idle mode supply current is measured with all output pins disconnected; xt al1 driven with t r = t f = 10ns; v il = v ss + 0.5v; v ih = v cc 0.5v; xtal2 not connected; ea = port 0 = v cc ; rst = v ss. 10. the power-down current is measured with all output pins disconnected, xt al2 not connected, ea = port 0 = v cc ; rst = v ss. 11. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 15ma maximum i ol per 8-bit port: 26ma maximum i ol total for all outputs: 67ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 12. pin capacitance for the ceramic dip package is 15pf maximum.
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 12 dc electrical characteristics for philips north america devices (sc80c31 and sc80c51) t amb = 0 c to +70 c or 40 c to +85 c, v cc = 5v 10%; v ss = 0v symbol parameter test conditions limits unit symbol parameter test conditions min typ 1 max unit v il input low voltage 4.5v < v cc < 5.5v 0.5 0.2v cc 0.1 v v ih input high voltage (ports 0, 1, 2, 3, ea ) 0.2v cc +0.9 v cc +0.5 v v ih1 input high voltage, xtal1, rst 0.7v cc v cc +0.5 v v ol output low voltage, ports 1, 2, 3 8 v cc = 4.5v i ol = 1.6ma 2 0.4 v v ol1 output low voltage, port 0, ale, psen 8, 7 v cc = 4.5v i ol = 3.2ma 2 0.4 v v oh output high voltage, ports 1, 2, 3 3 v cc = 4.5v i oh = 30 m a v cc 0.7 v v oh1 output high voltage (port 0 in external bus mode), ale 9 , psen 3 v cc = 4.5v i oh = 3.2ma v cc 0.7 v i il logical 0 input current, ports 1, 2, 3 v in = 0.4v 1 50 m a i tl logical 1-to-0 transition current, ports 1, 2, 3 6 v in = 2.0v see note 4 650 m a i li input leakage current, port 0 0.45 < v in < v cc 0.3 10 m a i cc power supply current (see figure 8): active mode @ 16mhz 5 idle mode @ 16mhz 5 power-down mode see note 5 t amb = 0 to +70 c t amb = 40 to +85 c 11.5 1.3 3 32 5 50 75 m a m a m a m a r rst internal reset pull-down resistor 40 225 k w c io pin capacitance 10 (except ea ) 15 pf notes: 1. t ypical ratings are not guaranteed. the values listed are at room temperature, 5v . 2. capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. in the worst cases (capacitive loading > 100pf), the noise pulse on the ale pin may exceed 0.8v . in such cases, it may be desirable to qualify ale with a schmitt trigger , or use an address latch with a schmitt t rigger strobe input. i ol can exceed these conditions provided that no single output sinks more than 5ma and no more than two outputs exceed the test conditions. 3. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the (v cc 0.7) specification when the address bits are stabilizing. 4. pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in is approximately 2v. 5. see figures 9 through 12 for i cc test conditions. active mode: i cc = 1.5 freq + 8.0; idle mode: i cc = 0.14 freq +2.31; see figure 8. 6. this value applies to t amb = 0 c to +70 c. for t amb = 40 c to +85 c, i tl = 750 m a. 7. load capacitance for port 0, ale, and psen = 100pf , load capacitance for all other outputs = 80pf . 8. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 15ma (*note: this is 85 c specification.) maximum i ol per 8-bit port: 26ma maximum total i ol for all outputs: 71ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 9. ale is tested to v oh1 , except when ale is off then v oh is the voltage specification. 10. pin capacitance is characterized but not tested. pin capacitance is less than 25pf . pin capacitance of ceramic package is less than 15pf (except ea it is 25pf).
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 13 ac electrical characteristics for sc87c51 1233mhz philips north america devices t amb = 0 c to +70 c or 40 c to +85 c, v cc = 5v 10%, v ss = 0v (sc87c51 12, 16 and 24mhz versions); for sc87c51 (33mhz only) t amb = = 0 c to +70 c, v cc = 5v 5% variable clock 3 symbol figure parameter min max unit 1/t clcl oscillator frequency: speed versions sc87c51 c g p y 3.5 3.5 3.5 3.5 12 16 24 33 mhz mhz mhz mhz t lhll 1 ale pulse width 2t clcl 40 ns t avll 1 address valid to ale low t clcl 13 ns t llax 1 address hold after ale low t clcl 20 ns t lliv 1 ale low to valid instruction in 4t clcl 65 ns t llpl 1 ale low to psen low t clcl 13 ns t plph 1 psen pulse width 3t clcl 20 ns t pliv 1 psen low to valid instruction in 3t clcl 45 ns t pxix 1 input instruction hold after psen 0 ns t pxiz 1 input instruction float after psen t clcl 10 ns t aviv 1 address to valid instruction in 5t clcl 55 ns t plaz 1 psen low to address float 10 ns data memory t rlrh 2, 3 rd pulse width 6t clcl 100 ns t wlwh 2, 3 wr pulse width 6t clcl 100 ns t rldv 2, 3 rd low to valid data in 5t clcl 90 ns t rhdx 2, 3 data hold after rd 0 ns t rhdz 2, 3 data float after rd 2t clcl 28 ns t lldv 2, 3 ale low to valid data in 8t clcl 150 ns t avdv 2, 3 address to valid data in 9t clcl 165 ns t llwl 2, 3 ale low to rd or wr low 3t clcl 50 3t clcl +50 ns t avwl 2, 3 address valid to wr low or rd low 4t clcl 75 ns t qvwx 2, 3 data valid to wr transition t clcl 20 ns t whqx 2, 3 data hold after wr t clcl 20 ns t rlaz 2, 3 rd low to address float 0 ns t whlh 2, 3 rd or wr high to ale high t clcl 20 t clcl +25 ns external clock t chcx 5 high time 12 ns t clcx 5 low time 12 ns t clch 5 rise time 20 ns t chcl 5 fall time 20 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100pf , load capacitance for all other outputs = 80pf . 3. for all philips north america speed versions only . 4. interfacing the 87c51 to devices with float times up to 50ns is permitted. this limited bus contention will not cause damage to port 0 drivers.
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 14 ac electrical characteristics for philips devices t amb = 0 c to +70 c, v cc = 5v 20%, v ss = 0v (pcb80c31/51, pcf80c31/51) 1, 2, 4, 5 variable clock 3 symbol figure parameter min max unit 1/t clcl oscillator frequency: speed versions pcb8031/51 2 pca/pcb/pcf80c31/51 3 pcb/pcf80c31/51 4 pcb/fb80c31/51 5 0.5 1.2 1.2 1.2 12 16 24 33 mhz mhz mhz mhz t lhll 1 ale pulse width 2t clcl 40 ns t avll 1 address valid to ale low t clcl 25 ns t llax 1 address hold after ale low t clcl 25 ns t lliv 1 ale low to valid instruction in 4t clcl 65 ns t llpl 1 ale low to psen low t clcl 25 ns t plph 1 psen pulse width 3t clcl 45 ns t pliv 1 psen low to valid instruction in 3t clcl 60 ns t pxix 1 input instruction hold after psen 0 ns t pxiz 1 input instruction float after psen t clcl 25 ns t aviv 1 address to valid instruction in 5t clcl 80 ns t plaz 1 psen low to address float 10 ns data memory t rlrh 2, 3 rd pulse width 6t clcl 100 ns t wlwh 2, 3 wr pulse width 6t clcl 100 ns t rldv 2, 3 rd low to valid data in 5t clcl 90 ns t rhdx 2, 3 data hold after rd 0 ns t rhdz 2, 3 data float after rd 2t clcl 28 ns t lldv 2, 3 ale low to valid data in 8t clcl 150 ns t avdv 2, 3 address to valid data in 9t clcl 165 ns t llwl 2, 3 ale low to rd or wr low 3t clcl 50 3t clcl +50 ns t avwl 2, 3 address valid to wr low or rd low 4t clcl 75 ns t qvwx 2, 3 data valid to wr transition t clcl 30 ns t whqx 2, 3 data hold after wr t clcl 25 ns t rlaz 2, 3 rd low to address float 0 ns t whlh 2, 3 rd or wr high to ale high t clcl 25 t clcl +25 ns external clock t chcx 5 high time 15 ns t clcx 5 low time 15 ns t clch 5 rise time 20 ns t chcl 5 fall time 20 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100pf , load capacitance for all other outputs = 80pf . 3. for all philips speed versions only. 4. interfacing the 80c31/51 to devices with float times up to 30ns is permitted. this limited bus contention will not cause damage to port 0 drivers. 5. v cc = 5v 10% for 33mhz.
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 15 ac electrical characteristics for philips north america devices (sc80c31 and sc80c51) t amb = 0 c to +70 c or 40 c to +85 c, v cc = 5v 10%, v ss = 0v 1, 2, 3 16mhz clock variable clock symbol figure parameter min max min max unit 1/t clcl 1 oscillator frequency speed versions : c, g 3.5 16 mhz t lhll 1 ale pulse width 85 2t clcl 40 ns t avll 1 address valid to ale low 22 t clcl 40 ns t llax 1 address hold after ale low 32 t clcl 30 ns t lliv 1 ale low to valid instruction in 150 4t clcl 100 ns t llpl 1 ale low to psen low 32 t clcl 30 ns t plph 1 psen pulse width 142 3t clcl 45 ns t pliv 1 psen low to valid instruction in 4 82 3t clcl 105 ns t pxix 1 input instruction hold after psen 0 0 ns t pxiz 1 input instruction float after psen 37 t clcl 25 ns t aviv 1 address to valid instruction in 4 207 5t clcl 105 ns t plaz 1 psen low to address float 10 10 ns data memory t rlrh 2, 3 rd pulse width 275 6t clcl 100 ns t wlwh 2, 3 wr pulse width 275 6t clcl 100 ns t rldv 2, 3 rd low to valid data in 147 5t clcl 165 ns t rhdx 2, 3 data hold after rd 0 0 ns t rhdz 2, 3 data float after rd 65 2t clcl 60 ns t lldv 2, 3 ale low to valid data in 350 8t clcl 150 ns t avdv 2, 3 address to valid data in 397 9t clcl 165 ns t llwl 2, 3 ale low to rd or wr low 137 239 3t clcl 50 3t clcl +50 ns t avwl 2, 3 address valid to wr low or rd low 122 4t clcl 130 ns t qvwx 2, 3 data valid to wr transition 13 t clcl 50 ns t whqx 2, 3 data hold after wr 13 t clcl 50 ns t qvwh 3 data valid to wr high 287 7t clcl 150 ns t rlaz 2, 3 rd low to address float 0 0 ns t whlh 2, 3 rd or wr high to ale high 23 103 t clcl 40 t clcl +40 ns external clock t chcx 5 high time 20 20 t clcl t clcx ns t clcx 5 low time 20 20 t clcl t chcx ns t clch 5 rise time 20 20 ns t chcl 5 fall time 20 20 ns shift register t xlxl 4 serial port clock cycle time 750 12t clcl ns t qvxh 4 output data setup to clock rising edge 492 10t clcl 133 ns t xhqx 4 output data hold after clock rising edge 8 2t clcl 117 ns t xhdx 4 input data hold after clock rising edge 0 0 ns t xhdv 4 clock rising edge to input data valid 492 10t clcl 133 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100pf , load capacitance for all other outputs = 80pf . 3. interfacing the 80c31/51 to devices with float times up to 45ns is permitted. this limited bus contention will not cause damage to port 0 drivers. 4. see application note an457 for external memory interfacing.
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 16 ac electrical characteristics for philips north america devices (sc80c31 and sc80c51) t amb = 0 c to +70 c or 40 c to +85 c, v cc = 5v 10%, v ss = 0v 1, 2, 3 24mhz clock variable clock 4 33mhz clock symbol figure parameter min max min max min max unit 1/t clcl 1 oscillator frequency speed versions : p (24mhz) : y (33mhz) 3.5 24 3.5 33 3.5 33 mhz t lhll 1 ale pulse width 43 2t clcl 40 21 ns t avll 1 address valid to ale low 17 t clcl 25 5 ns t llax 1 address hold after ale low 17 t clcl 25 ns t lliv 1 ale low to valid instruction in 102 4t clcl 65 55 ns t llpl 1 ale low to psen low 17 t clcl 25 5 ns t plph 1 psen pulse width 80 3t clcl 45 45 ns t pliv 1 psen low to valid instruction in 65 3t clcl 60 30 ns t pxix 1 input instruction hold after psen 0 0 0 ns t pxiz 1 input instruction float after psen 17 t clcl 25 5 ns t aviv 1 address to valid instruction in 128 5t clcl 80 70 ns t plaz 1 psen low to address float 10 10 10 ns data memory t rlrh 2, 3 rd pulse width 150 6t clcl 100 82 ns t wlwh 2, 3 wr pulse width 150 6t clcl 100 82 ns t rldv 2, 3 rd low to valid data in 118 5t clcl 90 60 ns t rhdx 2, 3 data hold after rd 0 0 0 ns t rhdz 2, 3 data float after rd 55 2t clcl 28 32 ns t lldv 2, 3 ale low to valid data in 183 8t clcl 150 90 ns t avdv 2, 3 address to valid data in 210 9t clcl 165 105 ns t llwl 2, 3 ale low to rd or wr low 75 175 3t clcl 50 3t clcl +50 40 140 ns t avwl 2, 3 address valid to wr low or rd low 92 4t clcl 75 45 ns t qvwx 2, 3 data valid to wr transition 12 t clcl 30 0 ns t whqx 2, 3 data hold after wr 17 t clcl 25 5 ns t qvwh 3 data valid to wr high 162 7t clcl 130 80 ns t rlaz 2, 3 rd low to address float 0 0 0 ns t whlh 2, 3 rd or wr high to ale high 17 67 t clcl 25 t clcl +25 5 55 ns external clock t chcx 5 high time 17 17 t clcl t clcx ns t clcx 5 low time 17 17 t clcl t chcx ns t clch 5 rise time 5 5 ns t chcl 5 fall time 5 5 ns shift register t xlxl 4 serial port clock cycle time 505 12t clcl 360 ns t qvxh 4 output data setup to clock rising edge 283 10t clcl 133 167 ns t xhqx 4 output data hold after clock rising edge 3 2t clcl 80 ns t xhdx 4 input data hold after clock rising edge 0 0 0 ns t xhdv 4 clock rising edge to input data valid 283 10t clcl 133 167 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100pf , load capacitance for all other outputs = 80pf . 3. interfacing the sc80c31/51 to devices with float times up to 45ns is permitted. this limited bus contention will not cause damage to port 0 drivers. 4. v ariable clock is specified for oscillator frequencies greater than 16mhz to 33mhz. for frequencies equal or less than 16mhz, see 16mhz aac electrial characteristicso, page 15.
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 17 explanation of the ac symbols each timing symbol has five characters. the first character is always `t' (= time). the other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. the designations are: a address c clock d input data h logic level high i instruction (program memory contents) l logic level low, or ale p psen q output data r rd signal t time v valid w wr signal x no longer a valid logic level z float examples: t avll = time for address valid to ale low. t llpl = time for ale low to psen low. t pxiz ale psen port 0 port 2 a0a15 a8a15 a0a7 a0a7 t avll t pxix t llax instr in t lhll t plph t lliv t plaz t llpl t aviv su00006 t pliv figure 1. external program memory read cycle t llax ale psen port 0 port 2 rd a0a7 from ri or dpl data in a0a7 from pcl instr in p2.0p2.7 or a8a15 from dph a0a15 from pch t whlh t lldv t llwl t rlrh t rlaz t avll t rhdx t rhdz t avwl t avdv t rldv su00007 figure 2. external data memory read cycle
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 18 t llax ale psen port 0 port 2 wr a0a7 from ri or dpl data out a0a7 from pcl instr in p2.0p2.7 or a8a15 from dph a0a15 from pch t whlh t llwl t wlwh t avll t avwl t qvwx t whqx su00008 figure 3. external data memory write cycle 0 1 2 3 4 5 6 7 8 instruction ale clock output data write to sbuf input data clear ri valid valid valid valid valid valid valid valid set ti set ri t xlxl t qvxh t xhqx t xhdx t xhdv su00027 1 2 3 0 4 5 6 7 figure 4. shift register mode timing v cc 0.5 0.45v 0.7v cc 0.2v cc 0.1 t chcl t clcl t clch t clcx t chcx su00009 figure 5. external clock drive
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 19 v cc 0.5 0.45v 0.2v cc +0.9 0.2v cc 0.1 note: ac inputs during testing are driven at v cc 0.5 for a logic `1' and 0.45v for a logic `0'. timing measurements are made at v ih min for a logic `1' and v il max for a logic `0'. su00010 figure 6. ac testing input/output v load v load +0.1v v load 0.1v v oh 0.1v v ol +0.1v note: timing reference points for timing purposes, a port is no longer floating when a 100mv change from load voltage occurs, and begins to float when a 100mv change from the loaded v oh /v ol level occurs. i oh /i ol 20ma. su00011 figure 7. float waveform 40 35 30 25 20 15 10 5 4mhz 8mhz 12mhz 16mhz freq at xtal1 max active mode (i ccmax = 1.43 freq + 1.9) typ active mode max idle mode typ idle mode i cc ma 20mhz 24mhz 45 30mhz 33mhz su00012 figure 8. i cc vs. freq v alid only within frequency specifications of the device under test
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 20 v cc p0 ea rst xtal1 xtal2 v ss v cc v cc v cc i cc (nc) clock signal su00719 figure 9. i cc test condition, active mode all other pins are disconnected v cc p0 ea rst xtal1 xtal2 v ss v cc v cc i cc (nc) clock signal su00720 figure 10. i cc test condition, idle mode all other pins are disconnected v cc 0.5 0.45v 0.7v cc 0.2v cc 0.1 t chcl t clcl t clch t clcx t chcx su00015 figure 11. clock signal waveform for i cc tests in active and idle modes t clch = t chcl = 5ns v cc p0 ea rst xtal1 xtal2 v ss v cc v cc i cc (nc) su00016 figure 12. i cc test condition, power down mode all other pins are disconnected. v cc = 2v to 5.5v
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 21 eprom characteristics the 87c51 is programmed by using a modified quick-pulse programming ? algorithm. it dif fers from older methods in the value used for v pp (programming supply voltage) and in the width and number of the ale/prog pulses. the 87c51 contains two signature bytes that can be read and used by an eprom programming system to identify the device. the signature bytes identify the device as an 87c51 manufactured by philips corporation. t able 3 shows the logic levels for reading the signature bytes, and for programming the program memory , the encryption table, and the security bits. the circuit configuration and waveforms for quick-pulse programming are shown in figures 13 and 14. figure 15 shows the circuit configuration for normal program memory verification. quick-pulse programming the setup for microcontroller quick-pulse programming is shown in figure 13. note that the 87c51 is running with a 4 to 6mhz oscillator . the reason the oscillator needs to be running is that the device is executing internal address and program data transfers. the address of the eprom location to be programmed is applied to ports 1 and 2, as shown in figure 13. the code byte to be programmed into that location is applied to port 0. rst , psen and pins of ports 2 and 3 specified in t able 3 are held at the `program code data' levels indicated in table 3. the ale/prog is pulsed low 25 times as shown in figure 14. t o program the encryption table, repeat the 25 pulse programming sequence for addresses 0 through 1fh, using the `pgm encryption t able' levels. do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. t o program the security bits, repeat the 25 pulse programming sequence using the `pgm security bit' levels. after one security bit is programmed, further programming of the code memory and encryption table is disabled. however, the other security bit can still be programmed. note that the ea /v pp pin must not be allowed to go above the maximum specified v pp level for any amount of time. even a narrow glitch above that voltage can cause permanent damage to the device. the v pp source should be well regulated and free of glitches and overshoot. program verification if security bit 2 has not been programmed, the on-chip program memory can be read out for program verification. the address of the program memory locations to be read is applied to ports 1 and 2 as shown in figure 15. the other pins are held at the `v erify code data' levels indicated in t able 3. the contents of the address location will be emitted on port 0. external pull-ups are required on port 0 for this operation. if the encryption table has been programmed, the data presented at port 0 will be the exclusive nor of the program byte with one of the encryption bytes. the user will have to know the encryption table contents in order to correctly decode the verification data. the encryption table itself cannot be read out. reading the signature bytes the signature bytes are read by the same procedure as a normal verification of locations 030h and 031h, except that p3.6 and p3.7 need to be pulled to a logic low . the values are: (030h) = 15h indicates manufactured by philips (031h) = 92h indicates 87c51 program/verify algorithms any algorithm in agreement with the conditions listed in t able 3, and which satisfies the timing specifications, is suitable. erasure characteristics erasure of the eprom begins to occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 angstroms. since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room level fluorescent lighting) could cause inadvertent erasure. for this and secondary effects, it is recommended that an opaque label be placed over the window. for elevated temperature or environments where solvents are being used, apply kapton tape fluorglas part number 23455, or equivalent. the recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrated dose of at least 15w -sec/cm 2 . exposing the eprom to an ultraviolet lamp of 12,000 m w/cm 2 rating for 20 to 39 minutes, at a distance of about 1 inch, should be sufficient. erasure leaves the array in an all 1s state. table 3. eprom programming modes mode rst psen ale/prog ea /v pp p2.7 p2.6 p3.7 p3.6 read signature 1 0 1 1 0 0 0 0 program code data 1 0 0* v pp 1 0 1 1 verify code data 1 0 1 1 0 0 1 1 pgm encryption table 1 0 0* v pp 1 0 1 0 pgm security bit 1 1 0 0* v pp 1 1 1 1 pgm security bit 2 1 0 0* v pp 1 1 0 0 notes: 1. `0' = v alid low for that pin, `1' = valid high for that pin. 2. v pp = 12.75v + 0.25v. 3. v cc = 5v 10% during programming and verification. 4. *ale/prog receives 25 programming pulses while v pp is held at 12.75v . each programming pulse is low for 100 m s ( 10 m s) and high for a minimum of 10 m s. ? t rademark phrase of intel corporation.
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 22 a0a7 1 1 1 46mhz +5v pgm data +12.75v 25 100 m s pulses to ground 0 1 0 a8a11 p1 rst p3.6 p3.7 xtal2 xtal1 v ss v cc p0 ea /v pp ale/prog psen p2.7 p2.6 p2.0p2.3 87c51 su00017 figure 13. programming configuration ale/prog: ale/prog: 1 0 1 0 25 pulses 100 m s+ 10 10 m s min su00018 figure 14. prog waveform a0a7 1 1 1 46mhz +5v pgm data 1 1 0 0 enable 0 a8a11 p1 rst p3.6 p3.7 xtal2 xtal1 v ss v cc p0 ea /v pp ale/prog psen p2.7 p2.6 p2.0p2.3 87c51 su00019 figure 15. program verification
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 23 eprom programming and verification characteristics t amb = 21 c to +27 c, v cc = 5v 10%, v ss = 0v (see figure 16) symbol parameter min max unit v pp programming supply voltage 12.5 13.0 v i pp programming supply current 50 ma 1/t clcl oscillator frequency 4 6 mhz t avgl address setup to prog low 48t clcl t ghax address hold after prog 48t clcl t dvgl data setup to prog low 48t clcl t ghdx data hold after prog 48t clcl t ehsh p2.7 (enable ) high to v pp 48t clcl t shgl v pp setup to prog low 10 m s t ghsl v pp hold after prog 10 m s t glgh prog width 90 110 m s t avqv address to data valid 48t clcl t elqz enable low to data valid 48t clcl t ehqz data float after enable 0 48t clcl t ghgl prog high to prog low 10 m s programming * verification * address address data in data out logic 1 logic 1 logic 0 t avqv t ehqz t elqv t shgl t ghsl t glgh t ghgl t avgl t ghax t dvgl t ghdx p1.0p1.7 p2.0p2.4 port 0 ale/prog ea /v pp p2.7 enable su00020 t ehsh note: * for programming verification see figure 13. for verification conditions see figure 15. figure 16. eprom programming and verification
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 24 0590b 40-pin (600 mils wide) ceramic dual in-line (f) package (with window (fa) package) notes: 1. controlling dimension: inches. millimeters are 2. dimension and tolerancing per ansi y14. 5m-1982. 3. ato, ado, and aeo are reference datums on the body 4. these dimensions measured with the leads 5. pin numbers start with pin #1 and continue 6. denotes window location for eprom products. and include allowance for glass overrun and meniscus on the seal line, and lid to base mismatch. constrained to be perpendicular to plane t. counterclockwise to pin #40 when viewed shown in parentheses. from the top. d pin # 1 e 0.225 (5.72) max. 0.010 (0.254) t e d 0.023 (0.58) 0.015 (0.38) 0.165 (4.19) 0.125 (3.18) 0.070 (1.78) 0.050 (1.27) t seating plane 0.620 (15.75) 0.590 (14.99) (note 4) 0.598 (15.19) 0.571 (14.50) bsc 0.600 (15.24) 0.695 (17.65) 0.600 (15.24) (note 4) 0.015 (0.38) 0.010 (0.25) 0.175 (4.45) 0.145 (3.68) 0.055 (1.40) 0.020 (0.51) 0.100 (2.54) bsc 2.087 (53.01) 2.038 (51.77) 0.098 (2.49) 0.040 (1.02) 0.098 (2.49) 0.040 (1.02) see note 6 8530590b 06688
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 25 1472a 44-pin cerquad j-bend (k) package notes: 1. all dimensions and tolerances to conform 2. uv window is optional. 3. dimensions do not include glass protrusion. glass protrusion to be 0.005 inches maximum 4. controlling dimension millimeters. 5. all dimensions and tolerances include lead trim of fset and lead plating finish. 6. backside solder relief is optional and dimensions are for reference only . 1.02 (0.040) x 45 16.89 (0.665) 16.00 (0.630) 17.65 (0.695) 17.40 (0.685) chamfer 45 16.89 (0.665) 16.00 (0.630) 17.65 (0.695) 17.40 (0.685) on each side. to ansi y14.51982. 2 3 3 x 0.63 (0.025) r min. 3.05 (0.120) 2.29 (0.090) 4.83 (0.190) 3.94 (0.155) seating plane 0.38 (0.015) 0.51 (0.02) x 45 6 6 17.65 (0.656) 17.40 (0.685) 1.27 (0.050) 12.7 (0.500) 8.13 (0.320) 7.37 (0.290) 40x 4.83 (0.190) 3.94 (0.155) seating plane 0.15 (0.006) min. 0.25 (0.010) r min. 0.508 (0.020) r min. 0.25 (0.010) 0.15 (0.006) 90 + 5 10 0.076 (0.003) min. detail b mm/(inch) see det ail b see det ail a detail a typ. all sides mm/(inch) 1.52 (0.060) ref . 0.482 (0.019 + 0.002) seating plane 1.02 + 0.25 (0.040 + 0.010) base plane 45 typ. 4 places 0.73 + 0.08 (0.029 + 0.003) 1.27 (0.050) typ. nominal 8.13 (0.320) 7.37 (0.290) 3 853-1472a 05854
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 26 dip40: plastic dual in-line package; 40 leads (600 mil) sot129-1
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 27 plcc44: plastic leaded chip carrier; 44 leads sot187-2
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 28 qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers 1996 aug 16 29 notes
philips semiconductors product specification 80c31/80c51/87c51 cmos single-chip 8-bit microcontrollers philips semiconductors and philips electronics north america corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. life support applications philips semiconductors and philips electronics north america corporation products are not designed for use in life support appliances, devices, or systems where malfunction of a philips semiconductors and philips electronics north america corporation product can reasonably be expected to result in a personal injury . philips semiconductors and philips electronics north america corporation customers using or selling philips semiconductors and philips electronics north america corporation products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors and philips electronics north america corporation for any damages resulting from such improper use or sale. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 definitions data sheet identification product status definition objective specification preliminary specification product specification formative or in design preproduction product full production this data sheet contains the design target or goal specifications for product development. specifications may change in any manner without notice. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. philips semiconductors and philips electronics north america corporation register eligible circuits under the semiconductor chip protection act. ? copyright philips electronics north america corporation 1996 all rights reserved. printed in u.s.a.

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